Designing data processors for use in mobile stations is inherently difficult due to the tradeoffs that must always be made between competing considerations, including energy efficiency, computation power, and flexibility. Most current multi-standard wireless devices comprise blocks of separate and largely independent ASIC devices, each of which is related to a different wireless standard. The separate ASIC devices are stacked together in order to provide support for several wireless standards simultaneously. However, this approach results in increased die size, increased power consumption, and lack of flexibility.
As an alternative, software-defined radio (SDR) devices may be used. SDR devices use reconfigurable hardware that may be programmed over the air to operate under different wireless protocols. For example, an SDR transceiver in a wireless laptop computer may be configured by a first software load to operate in a CDMA2000 wireless network and may be reconfigured by a second software load to operate in an HSDPA wireless network. SDR systems minimize cost (design time, TTM) and power consumption, while maximizing flexibility, thereby providing an optimized combination of scalability and modularity.
One such approach involves a re-configurable correlation unit that may be implemented in a context-based operation reconfigurable instruction set processor, as disclosed in U.S. patent application Ser. No. 11/150,511, incorporated by reference above. Such a correlation unit matches the architecture to the domain of application and optimizes the performance and power jointly. Thus, the real-time processing requirements and low-power requirements of wireless mobile stations are met simultaneously. The correlation unit is highly re-configurable and may be used for different functional blocks operating under different standards.
However, in the case of High-Speed Data Packet Access (HSDPA) or other multi-code applications, the same data has to be entered multiple times into a same correlator cell in order to process the different HSDPA (or other multi-code standard) symbols. Entering the same input data stream over and over into the same cell in this manner increases the power of the input bus and complicates the addressing to the input memory block, resulting in an increase in die area and power consumption. Therefore, there is a need in the art for a multi-code correlation architecture for use in SDR systems that operates without requiring the same data to be entered into a correlator cell multiple times.